# All digital modulation and demodulation with block diagram explanation

This article will contain, all the popular types of digital modulation and demodulation techniques such as BASK, BFSK, BPSK, DM, ADM, etc.

*Note: This is a note that I had made while studying the course, it was written for reference for myself and I don’t assure the accuracy of the content. I don’t recommend using this as an authentic source of reference. Images credit goes to the course instructor, Assistant Professor Brajesh Mishra. *

**ASK Modulator (Amplitude Shift Keying Modulator)**

A continuous high-frequency carrier is fed. Modulating digital signal is the binary sequence from the message signal making the unipolar input to be either High or Low. The high signal closes the switch, allowing a carrier wave. Hence, the output will be the carrier signal at high input. When there is low input, the switch opens, allowing no voltage to appear. Hence, the output will be low.

So for High (1) switch closes and the carrier signal is the output and for Low (0), the switch opens and hence the output is 0.

**ASK Demodulation (Asynchronous or Non-Coherent)**

The first block we see is the adder, which adds noise to the ASK signal. After that, the ASK signal is passed through Band Pass Filter which only allows the fixed band of our concern to pass through. Then the signal is passed through the rectifier. The rectified output only consists of high-frequency positive wave output. In order to smooth, the signal this rectified signal is further passed through LPF to suppress the high-frequency component-giving rise to an envelope-detected signal. The higher amplitude rectified signals, the filtered output will be of high amplitude and for lower amplitude rectified carrier signals, the filtered output will be of low amplitude constant signal. The combination of Rectifier and LPF circuit is also called envelope detector.

Hence, finally, a comparator or the Decision-making device gives output as 1 or 0 for high amplitude and low reference amplitude respectively.

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**ASK Demodulation (Synchronous or Coherent)**

The first block we see in the demodulation method is the mixer. To one input of a mixer, the ASK modulated wave is applied whereas to its other input synchronous carrier is applied. This carrier can be generated either at the receiver or can be extracted from the modulated signal itself using a different recovery circuit. The output of a mixer is the product of an ASK signal and a carrier which consist of DC components along with a high-frequency signal. The signal is then integrated using an integrator from 0 to Tb (Bit Duration, ie. One-bit period). Which gives a signal which can be compared with the threshold value and could be concluded as 1 or 0 with respect to the threshold value in the decision-making block. Hence, finally, a comparator or the Decision-making device gives output as 1 or 0 for high amplitude and low reference amplitude respectively.

**BFSK (Binary Frequency Shift Keying) Modulator **

The frequency is selected such that the signals are orthonormal to each other. When two orthonormal signals is multiplied and integrated we get the integration output as 0. Each mixer (multiplier) in the upper path and lower path are fed with ø1 and ø2 which are the orthonormal basic function.

First, the binary input is fed.

*Case 1: Input is 1.*

Traveling through the upper path, the input 1 gets multiplied with ø1 and we get ø1, as output in the upper path. While traveling through the lower path the input gets inverted as there is an inverter block in between and the input 1 becomes 0, 0 now when multiplied with the basic function we get 0 from the lower path. So when both paths are added in the adder block we get ø1 as output.

*Case 2: Input is 0*

Similarly, as above, 0 as input makes the upper path 0 and lower path ø2.

So, when 1 is the input we get ø1 and 0 is the input we get ø2, which are in fact two frequency carriers. In this way, we get two-frequency signals for two inputs (1 and 0).

**BFSK (Binary Frequency Shift Keying) Receiver (Synchronous)**

The frequency is selected such that the signals are orthonormal to each other. When two orthonormal signals are multiplied and integrated we get the integration output as 0.

The received signal x(t) is the combination of signal S(t) and white noise. The received signal is then fed in the upper and lower path which consists of multiplier and integrator. X1 is for upper path output and X2 is for lower path output. Then in the next block, subtraction is done such that, r= x1-x2. The following signal is fed to the decision-making device. If r>0, it is interpreted as 1 and if r <= 0, output is 0.

Here, if the input signal is S1, in the upper path it is multiplied with ø1 and integrated which gives output √Eb. In the lower path, S1 is multiplied with ø2 and integrated which gives 0 (Due to orthonormality). So, r= √Eb – 0 = √Eb.

Which is interpreted as 1 by the decision-making device.

But if S2 is the input signal then the upper path (x1) becomes zero due to orthonormality and the lower path (x2) becomes √Eb. So, r= 0-√Eb = -√Eb.

This is interpreted as 0 by the decision-making device.

From the above-discussed process, we demodulate the signal and obtain it in binary form.

**BPSK(Binary Phase Shift Keying) Modulation**

First, by using symbol mapping binary bits 1 and 0 are represented by the transmission symbols 1 and -1 respectively. Which is shown in the diagram as a binary signal in polar form. The binary signal in polar form and ø1 (basis function) are multiplied using a product modulator.

If the data to be modulated is 1, 1 is multiplied with ø1, which gives √Eb*ø1 as the modulated output, whereas if data to be modulated is 0, -1 is multiplied with ø1, which gives -√Eb*ø1, which are the modulated waveform of the BPSK modulator.

**BPSK(Binary Phase Shift Keying) Receiver (Synchronous)**

The received modulated waveform, x(t), is multiplied with the basis function and is integrated. The modulated waveform is either positive or negative, ie. √Eb*ø1 or -√Eb*ø1, which when integrated also gives some positive value or negative value. The integrated output is then fed to the comparator or the decision-making device which, if x1(t) is greater than 0, gives demodulated data as 1 and if x1(t) is less than or equal to zero gives the demodulated data as 0.

In this way, the demodulation of the BPSK modulated wave is done in the synchronous detector.

**QPSK (Quadrature Phase Shift Keying) Modulator**

Here, the input binary signal is fed to the demultiplexer, which sends one bit (even) in the upper branch and another bit (odd) in the lower branch. Also, 1 is represented as 1 whereas 0 is represented as -1, using symbol mapping.

Suppose our input binary signal is 10. Let’s consider 0 as even and 1 as an odd bit. Even bit is transmitted in the upper branch which is 0 but is mapped as -1. It gets multiplied with ø1, which gives us a negative value, whereas the even bit is transmitted in the lower branch, i.e 1 is multiplied with ø2, which gives us a positive value. Finally, both get added to the adder. We get the expression in the form (+or – √E cos(a) +or – √E sin(b)). Which is the modulated output of the QPSK modulator circuit. Similar is for other inputs, 11, 00, and 01.

**QPSK(Quadrature Phase Shift Keying) Demodulation**

Here, ø1 and ø2 are orthonormal basis functions. First of all the received signal which is the expression in the form (+or – √E cos(a) +or – √E sin(b)), is fed in the upper and the lower path. In the upper path, it is multiplied with ø1 and integrated, which in fact cancels out the ø2 term due to orthonormality property. Which eventually gives only the multiplied and integrated term of ø1. Likewise in the lower path too, the received equation is fed and multiplied with ø2 and integrated which in fact cancels out the ø1 term of the equation and the remaining is the integrated term of ø2. Using the mapping table the decision-making device then concludes the integrated term as either 0 or 1. Which is then multiplexed using a multiplexer which eventually gives the two-digit binary output as desired, either 00, 10, 01, or 11.

**QAM(Quadrature Amplitude Modulation) Transmitter**

The Serial to Parallel Converter groups the incoming data into quadbits. Each quadbit consists of a pair of digits, which can be called the most significant digit (MSD) and the least significant digit (LSD). The MSD is sent to the I-channel of the modulator; the LSD is sent to the Q-channel of the modulator. Each channel of the modulator works independently to processes the data it receives. The 2 to L level converter converts the 2-bit binary signal to 4 levels (suppose here). Each of the four levels represents a specific digit. The four levels used are proportional to -3, -1, +1, and +3. This makes the distribution of the constellation points uniform.

After that, each mixer in the upper path, as well as the lower path, performs modulation by multiplying the sinusoidal carrier (upper cos, and lower sin function carrier) by the four-level data signal. Multiplying the carrier by ±1 causes a 180degree phase shift in the mixer output signal and is equivalent to BPSK modulation. Multiplying by +3 causes a three-fold increase in peak amplitude and is essentially a type of ASK modulation. Multiplying the carrier by -3 causes a 180-degree phase shift and a threefold increase in peak amplitude. The mixer output signal is therefore a bi-phase, bi-level sinusoidal signal. Which is then summed using adder. The final received signal is the QAM modulated signal.

**QAM(Quadrature Amplitude Modulation) Receiver**

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The received QAM signal is a bi-phase, bi-level sinusoidal signal. The signal is fed to the upper and the lower branch. In the upper path, the signal is multiplied with the cos carrier signal, and integrated which gives us the expression. Similarly, in the lower path, the signal is multiplied with the sin carrier signal, and integrated which also gives the expression. The expression is then fed to the decision-making device which has an L-1 threshold, which means here if we have supposed L=4, there are 3 thresholds. Using the four levels done during modulation as the reference which is proportional to -3, -1, +1, and +3 (which makes the distribution of the constellation points uniform), the decision is taken. The decision-making device gives the 2 most significant bits from one path and the 2 least significant from another path. The MSB and LSB bits are then combined in the multiplexer block which eventually gives us back our 4-bit binary signal. With the process explained above the expression (modulated QAM) is converted to a 4-bit binary signal (demodulated QAM).

**DPCM (Differential Pulse Code Modulation) Transmitter.**

The block diagram of the DPCM transmitter consists of Quantizer and Predictor with two summer circuits. The first comparator (summer) has sampled input as input and the subtraction of the predicted signal. Here, the predictor produces the assumed samples from the previous outputs of the transmitter circuit. The quantizer output signal and the previous prediction is added and given as input to the prediction filter. This makes the prediction closer to the actually sampled signal. The quantized error signal is very small and can be encoded by using a small number of bits. Thus the number of bits per sample is reduced in DPCM. The comparator finds out the difference between the actual sample value and the predicted value. This is called signal error and it is denoted as e(nTs).

The same predictor circuit is used in the decoder to reconstruct the original input.

The quantized version of the signal is the sum of the original sample value and quantized error. The quantized error can be positive or negative. This signal from the quantizer is then encoded using an encoder which is the final DPCM modulated signal.

**DPCM ****(Differential Pulse Code Modulation) ****Receiver**

The block diagram of the DPCM receiver uses the same predictor circuit as in the decoder to reconstruct the original input. The block diagram consists of a decoder and prediction filter. In the absenteeism of noise, the encoded receiver input will be the same as the encoded transmitter output. The predictor undertakes a value, based on the previous outputs. The input given to the decoder is the received modulated DPCM signal which is processed and that output is summed up with the output of the predictor, to obtain better output. This means here first of all the decoder will reconstruct the quantized form of the original signal. Therefore the signal at the receiver differs from the actual signal by quantization error, which is introduced permanently in the reconstructed signal. In this way, the original signal with quantization error is obtained which is then demodulated form or the output of the DPCM receiver.

**Delta Modulation Transmitter**

The delta modulation transmitter consists of a 1-bit quantizer and a delay circuit along with two summer circuits.

Delta modulation transmits only one bit per sample. The present sample value is compared with the previous sample value and this result whether the amplitude is increased or decreased is transmitted.

The input signal is approximated to step signal by the delta modulator. This step size is kept fixed. The difference between the input signal and staircase approximated signal is confined to two levels, i.e., +delta and -delta.

If the difference is positive, then approximated signal is increased by one step and if the difference is negative, then approximated signal is reduced by one step. When the step is reduced, ‘0’ is transmitted and if the step is increased, ‘1’ is transmitted.

Here in the block diagram, the summer in the accumulator adds quantizer output with the previous sample approximation, which gives the present sample approximation. The previous sample approximation is restored by delaying one sample period Ts

The samples input signal x(nTs) and staircase approximated signal xˆ(nTs ) are subtracted to get error signal e(nTs ).

Thus, depending on the sign of e(nTs ), a one-bit quantizer generates an output of +delta or -delta.

If the step size is +delta, then binary ‘1’ is transmitted and if it is -delta, then binary ‘0’ is transmitted. Therefore, for each sample, only one binary bit is transmitted.

In this way, the modulated wave is transmitted using a DM transmitter.

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**DM Receiver**

The block diagram of the Delta Modulation receiver consists of a low pass filter(LPF), a summer, and a delay circuit. The predictor circuit is eliminated here and hence no assumed input is given to the demodulator.

The input is the delta modulated waveform, which in fact consists of 0 or 1 which means +delta or –delta. The accumulator generates the staircase approximated signal output and is delayed by one sampling period Ts. It is then added to the input signal. If the input is binary ‘1’ then it adds a +delta step to the previous output (which is delayed). If the input is binary ‘0’ then one step ‘delta’ is subtracted from the delayed signal. Hence we obtain the staircase signal. The signal is then smoothed using a low pass filter. LPF smoothens the staircase signal to reconstruct the original message signal x(t).

In this way the demodulation of Delta Modulated wave is done.

**Adaptive Delta Modulation Transmitter**

The block diagram of the transmitter circuit consists of a summer, quantizer, Delay circuit, and a logic circuit for step size control. We know that this Modulation method is similar to Delta modulation except that the step size is variable according to the input signal in Adaptive Delta Modulation whereas it is a fixed value in delta modulation. The baseband signal X(nTs) is given as input to the circuit in the summer. The feedback circuit present in the transmitter is an Integrator. The integrator generates the staircase approximation of the previous sample.

At the summer circuit, the difference between the present sample and staircase approximation of previous sample e(nTs) is calculated. This error signal is passed to the quantizer, where a quantized value is generated. The step size control block controls the step size of the next approximation based on either the quantized value is high or low. Which ultimately generates the variable step size i.e. if the segment is steep step size is increased and if the signal is varying slowly the step size is reduced. Finally, The quantized signal is given as output. Which is the modulated output of Adaptive delta modulation.

**Adaptive Delta Modulation Receiver**

The block diagram of the Adaptive Delta Modulation receiver has two main parts. Using these blocks and Low pass filter demodulation takes place.

The first part is the step size control. Here the received signal is passed through a logic step size control block, where the step size is produced from each incoming bit. Step size is decided based on present and previous input.

In the second part of the receiver block, the accumulator circuit recreates the staircase signal which was variable step size.

Finally, the waveform is then applied to a low pass filter which smoothens the waveform and recreates the original signal. In this was the demodulation process is done on the receiver side.

*Note: This is a note that I had made while studying the course, it was written for reference for myself and I don’t assure the accuracy of the content. I don’t recommend using this as an authentic source of reference. Images credit goes to the course instructor, Assistant Professor Brajesh Mishra. *

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